The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2025
Filed:
Nov. 17, 2023
Applicant:
Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US);
Inventors:
Guilian Gao, Campbell, CA (US);
Cyprian Emeka Uzoh, San Jose, CA (US);
Jeremy Alfred Theil, Mountain View, CA (US);
Belgacem Haba, Saratoga, CA (US);
Rajesh Katkar, Milpitas, CA (US);
Assignee:
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/76898 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/08 (2013.01); H01L 24/95 (2013.01);
Abstract
Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.