The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Jan. 31, 2023
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Hang-Ting Lue, Hsinchu County, TW;

Tzu-Hsuan Hsu, Chiayi County, TW;

Teng-Hao Yeh, Hsinchu County, TW;

Chih-Chang Hsieh, Hsinchu, TW;

Chun-Hsiung Hung, Hsin-Chu, TW;

Yung-Chun Li, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/16 (2006.01); G06F 3/06 (2006.01); G06F 7/49 (2006.01); G06N 3/00 (2023.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/28 (2006.01); G11C 27/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0679 (2013.01); G06F 7/49 (2013.01); G06F 17/16 (2013.01); G06N 3/00 (2013.01); G11C 7/062 (2013.01); G11C 7/1006 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); G11C 16/0466 (2013.01); G11C 16/24 (2013.01); G11C 16/28 (2013.01); G11C 27/005 (2013.01);
Abstract

A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.


Find Patent Forward Citations

Loading…