The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Oct. 10, 2023
Applicant:

Hrl Laboratories, Llc, Malibu, CA (US);

Inventors:

Christopher Bohn, Santa Monica, CA (US);

Maxwell Choi, Thousand Oaks, CA (US);

Melanie Yajima, Los Angeles, CA (US);

Sieu Ha, Los Angeles, CA (US);

Maggy Lau, Stevenson, CA (US);

Clayton Jackson, Los Angeles, CA (US);

Wonill Ha, Thousand Oaks, CA (US);

Matthew Borselli, Calabasas, CA (US);

Assignee:

HRL LABORATORIES, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J 37/317 (2006.01); G03F 9/00 (2006.01); H01L 21/033 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01J 37/3177 (2013.01); G03F 9/7076 (2013.01); G03F 9/708 (2013.01); G03F 9/7088 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 23/544 (2013.01); H01J 2237/24475 (2013.01); H01J 2237/334 (2013.01); H01L 2223/54426 (2013.01);
Abstract

One or more embodiments of the present disclosure are directed toward improved methods of fabricating a semiconductor device utilizing multi-level electron beam lithography (e-beam lithography), an alignment marker for multi-level e-beam lithography, and a semiconductor device including the alignment marker. A method of fabricating a semiconductor device may include: forming an alignment marker in a substrate, the alignment marker including tantalum; determining, utilizing a backscatter electron detector of an electron beam lithography tool, a location of an edge of the alignment marker based on an atomic number contrast between the alignment marker and the substrate; and forming, utilizing the electron beam lithography tool, at least one transistor in the substrate based on the location of the edge of the alignment marker.


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