The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Jul. 28, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Sheng-Hsiung Chen, Zhubei, TW;

Chun-Chen Chen, Hsinchu, TW;

Shao-huan Wang, Hsinchu, TW;

Kuo-Nan Yang, Hsinchu, TW;

Chung-Hsing Wang, Hsinchu, TW;

Ren-Zheng Liao, Hsinchu, TW;

Meng-Xiang Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 111/04 (2020.01); G06F 117/12 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2117/12 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01);
Abstract

An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.


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