The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

May. 20, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Chin Hui Chong, Singapore, SG;

Seng Kim Ye, Singapore, SG;

Kelvin Tan Aik Boo, Singapore, SG;

Hong Wan Ng, Singapore, SG;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 25/50 (2013.01); H01L 2224/48011 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/48221 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/49052 (2013.01); H01L 2224/49177 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06562 (2013.01);
Abstract

A semiconductor package including a package substrate with an upper surface, a controller, and a die stack. The controller and the die stack are at the upper surface. The die stack includes a shingled sub-stack of semiconductor dies, a reverse-shingled sub-stack of semiconductor dies, and a bridging chip. The bridging chip is bonded between the shingled sub-stack and the reverse-shingled sub-stack, and has an internal trace. A first wire segment is bonded between the controller and a first end of the bridging chip, and a second wire segment is bonded between a second end of the bridging chip and each semiconductor die of the shingled sub-stack. The internal trace electrically couples the first and second wire segments. Additionally, a third wire segment is bonded between the controller and each semiconductor die of the reverse-shingled sub-stack.


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