The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Jul. 12, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Cheng-Yu Yang, Changhua County, TW;

Chia-Ta Yu, Hsinchu, TW;

Kai-Hsuan Lee, Hsinchu, TW;

Sai-Hooi Yeong, Hsinchu County, TW;

Feng-Cheng Yang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device includes a substrate and two fins protruding from the substrate. Each fin includes two source/drain (S/D) regions and a channel region. Each fin includes a top surface that remains flat across the S/D regions and the channel region. The semiconductor device also includes a gate stack engaging each fin at the respective channel region, a first dielectric layer on sidewalls of the gate stack, a first epitaxial layer over top and sidewall surfaces of the S/D regions of the two fins, and a second epitaxial layer over top and sidewall surfaces of the first epitaxial layer.


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