The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Jul. 28, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Gulbagh Singh, Tainan, TW;

Kun-Tsang Chuang, Miaoli, TW;

Po-Jen Wang, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/74 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/482 (2006.01); H01L 23/485 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/743 (2013.01); H01L 21/76802 (2013.01); H01L 21/7682 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/4821 (2013.01); H01L 23/485 (2013.01); H01L 23/5222 (2013.01); H01L 23/5223 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53295 (2013.01); H01L 27/1203 (2013.01);
Abstract

The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.


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