The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Aug. 25, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Julien Frougier, Albany, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Andrew M. Greene, Slingerlands, NY (US);

Veeraraghavan S. Basker, Schenectady, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor device fabricated by forming FET fins from a layered semiconductor structure. The layered semiconductor structure incudes a sacrificial layer. Further by forming dummy gate structures on the FET fins, recessing the FET fins between dummy gate structures, growing source-drain regions between FET fins and the sacrificial layer, replacing active region dummy gate structures with high-k metal gates structures, and replacing the sacrificial layer with a dielectric isolation material, wherein the dielectric isolation material extends across the active region.


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