The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Apr. 15, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Yu-Chu Lin, Tainan, TW;

Chi-Chung Jen, Kaohsiung, TW;

Wen-Chih Chiang, Hsinchu, TW;

Yi-Ling Liu, Hsinchu, TW;

Huai-Jen Tung, Tainan, TW;

Keng-Ying Liao, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 41/30 (2023.01);
U.S. Cl.
CPC ...
H01L 29/7883 (2013.01); H01L 21/26513 (2013.01); H01L 29/40114 (2019.08); H01L 29/41725 (2013.01); H01L 29/42324 (2013.01); H01L 29/66492 (2013.01); H01L 29/66825 (2013.01); H01L 29/7833 (2013.01); H10B 41/30 (2023.02);
Abstract

A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.


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