The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2025
Filed:
Apr. 25, 2023
Adeia Semiconductor Solutions Llc, San Jose, CA (US);
Christopher J. Penny, Saratoga Springs, NY (US);
Benjamin D. Briggs, Waterford, NY (US);
Huai Huang, Saratoga, NY (US);
Lawrence A. Clevenger, Rhinebeck, NY (US);
Michael Rizzolo, Albany, NY (US);
Hosadurga Shobha, Niskayuna, NY (US);
Adeia Semiconductor Solutions LLC, San Jose, CA (US);
Abstract
A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.