The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Jun. 19, 2023
Applicant:

Parabellum Strategic Opportunities Fund Llc, Wilmington, DE (US);

Inventors:

Yu-Hsiang Hu, Hsinchu, TW;

Chen-Hua Yu, Hsinchu, TW;

Hung-Jui Kuo, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/027 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/0274 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/56 (2013.01); H01L 21/6835 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/211 (2013.01); H01L 2224/221 (2013.01);
Abstract

A chip package includes a semiconductor die laterally encapsulating by an insulating encapsulant, a first dielectric portion, conductive vias, conductive traces and a second dielectric portion. The first dielectric portion covers the semiconductor die and the encapsulant. The conductive vias penetrate through the first dielectric portion and electrically connected to the semiconductor die. The conductive traces are disposed on the first dielectric portion. The second dielectric portion is disposed on the first dielectric portion and covering the conductive traces, wherein a first minimum lateral width of a conductive trace among the conductive traces is smaller than a second minimum lateral width of a conductive via among the conductive vias. A method of forming the chip package is also provided.


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