The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Jul. 29, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Veronica Strong, Hillsboro, OR (US);

Aleksandar Aleksov, Chandler, AZ (US);

Henning Braunisch, Phoenix, AZ (US);

Brandon Rawlings, Chandler, AZ (US);

Johanna Swan, Scottsdale, AZ (US);

Shawna Liff, Scottsdale, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/24 (2013.01); H01L 24/73 (2013.01); H01L 24/82 (2013.01); H01L 25/105 (2013.01); H05K 1/181 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/73259 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10734 (2013.01);
Abstract

An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.


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