The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Jul. 26, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsin-Wen Su, Yunlin County, TW;

Chih-Chuan Yang, Tainan, TW;

Shih-Hao Lin, Hsinchu, TW;

Yu-Kuan Lin, Taipei, TW;

Lien-Jung Hung, Taipei, TW;

Ping-Wei Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01);
Abstract

A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.


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