The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2025
Filed:
Mar. 23, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Harry-Hak-Lay Chuang, Zhubei, TW;
Wei-Cheng Wu, Zhubei, TW;
Wen-Tuo Huang, Tainan, TW;
Chia-Sheng Lin, Tainan, TW;
Wei Chuang Wu, Tainan, TW;
Shih Kuang Yang, Tainan, TW;
Chung-Jen Huang, Tainan, TW;
Shun-Kuan Lin, Tainan, TW;
Chien Lin Liu, Kaohsiung, TW;
Ping-Tzu Chen, Tainan, TW;
Yung Chun Tu, Kaohsiung, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.