The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Jul. 28, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tsu-Hui Su, Taipei, TW;

Chun-Hsiang Fan, Hsinchu, TW;

Yu-Wen Wang, New Taipei, TW;

Ming-Hsi Yeh, Hsinchu, TW;

Kuo-Bin Huang, Jhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/66 (2006.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/30604 (2013.01); H01L 21/76224 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 22/12 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.


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