The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Jan. 13, 2023
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Weibing Shang, Hefei, CN;

Hongwen Li, Hefei, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 29/52 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01);
Abstract

The present disclosure provides a memory bank and a memory, relating to the technical field of semiconductors. The memory bank includes: multiple memory arrays arranged along a first direction, configured to store data and check codes, and each of the memory arrays being divided into at least two array units; multiple read-write control circuits, in one-to-one correspondence to the memory arrays, and the read-write control circuit being configured to write the data and the check codes to a corresponding memory array or read the data and the check codes from the corresponding memory array; the read-write control circuit being electrically connected to the array units through different data signal lines, and the read-write control circuit being configured to access only one of the array units in the corresponding memory array at a time; and multiple error checking and correcting units, electrically connected to the multiple read-write control circuits.


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