The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Aug. 29, 2022
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Abu Naser Zainuddin, Milpitas, CA (US);

Jiahui Yuan, Fremont, CA (US);

Towhidur Razzak, Santa Clara, CA (US);

Assignee:

SanDisk Technologies LLC, Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 29/12 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0433 (2013.01); G06F 3/0625 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/3459 (2013.01); G11C 29/12005 (2013.01); H01L 25/0657 (2013.01); H01L 24/08 (2013.01);
Abstract

Different ramp rates for different regions, or zones, of word lines are used for the pass voltage applied to unselected word lines during a program operation. The properties of the word lines, such as their resistance and capacitance (RC) values, vary across the NAND memory array. By determining the RC values of the word lines across the array, the word lines can be broken into multiple zones based on these properties. The zones can then be individually assigned different ramp rates for applying a pass voltage to the unselected word lines, where a parameter for the ramp rates can be stored as a register value on the memory die.


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