The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Jun. 23, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chun-Chieh Wang, Kaohsiung, TW;

Sheng-Wei Yeh, Taichung, TW;

Yueh-Ching Pai, Taichung, TW;

Chi-Jen Yang, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 29/16 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 23/532 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/76829 (2013.01); H01L 21/76841 (2013.01); H01L 21/76846 (2013.01); H01L 21/76849 (2013.01); H01L 29/1604 (2013.01); H01L 29/49 (2013.01); H01L 29/66795 (2013.01); H01L 23/53266 (2013.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01);
Abstract

Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.


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