The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Jun. 26, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ryan Hickey, Portland, OR (US);

Glenn A. Glass, Portland, OR (US);

Anand S. Murthy, Portland, OR (US);

Rushabh Shah, Hillsboro, OR (US);

Ju-Hyung Nam, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/167 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 29/42392 (2013.01); H01L 29/7853 (2013.01); H01L 29/78696 (2013.01); H01L 29/167 (2013.01);
Abstract

Gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. Individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire.


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