The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Jun. 06, 2023
Applicant:

Mediatek Inc., Hsinchu, TW;

Inventors:

Hsing-Chih Liu, Hsinchu, TW;

Zheng Zeng, San Jose, CA (US);

Che-Hung Kuo, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/5385 (2013.01); H01L 23/5389 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01);
Abstract

A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.


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