The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Jan. 25, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jui Fu Hsieh, Zhubei, TW;

Chia-Chi Yu, New Taipei, TW;

Chih-Teng Liao, Hsinchu, TW;

Yi-Jen Chen, Hsinchu, TW;

Chia-Cheng Tai, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 22/26 (2013.01); H01L 21/31116 (2013.01);
Abstract

A method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. The wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. The method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. The end point is an expected time point. The plurality of dielectric regions are etched to the target etching depth. The etching of the plurality of dielectric regions is stopped at the end point.


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