The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2024

Filed:

Aug. 25, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chieh-Fei Chiu, Tainan, TW;

Wen-Ting Chu, Kaohsiung, TW;

Yong-Shiuan Tsair, Tainan, TW;

Yu-Wen Liao, New Taipei, TW;

Chin-Yu Mei, Hsin-Chu, TW;

Po-Hao Tseng, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10N 70/00 (2023.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H10N 70/8265 (2023.02); H01L 23/3114 (2013.01); H01L 23/481 (2013.01); H01L 23/4952 (2013.01); H10N 70/841 (2023.02);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.


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