The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2024
Filed:
Apr. 25, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Ming-Chang Wen, Kaohsiung, TW;
Kuo-Hsiu Hsu, Zhongli, TW;
Jyun-Yu Tian, Hsinchu, TW;
Wan-Yao Wu, Hsinchu, TW;
Chang-Yun Chang, Taipei, TW;
Hung-Kai Chen, Taichung, TW;
Lien Jung Hung, Taipei, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.