The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

Apr. 11, 2024
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Johnatan Avraham Kantarovsky, South Burlington, VT (US);

Rajendran Krishnasamy, Essex Junction, VT (US);

Mark D. Levy, Williston, VT (US);

John J. Ellis-Monaghan, Grand Isle, VT (US);

Michael J. Zierak, Colchester, VT (US);

Kristin Marie Welch, Essex, VT (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 29/20 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 29/404 (2013.01); H01L 29/2003 (2013.01); H01L 29/401 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01);
Abstract

Disclosed are a structure with a multi-level field plate and a method of forming the structure. The field plate includes multiple first conductors on a dielectric layer and separated from each other by spaces with different widths (e.g., by with progressively decreasing widths). A conformal additional dielectric layer extends over the first conductors and onto the dielectric layer within the spaces. The field plate also includes, on the additional dielectric layer, second conductor(s) with portions thereof extending into the spaces. Within the spaces, the second conductor portions are at different heights (e.g., at progressively increasing heights) above the dielectric layer. Such a field plate can be incorporated into a transistor (e.g., a high electron mobility transistor (HEMT)) to, not only reduce the peak of an electric field exhibited proximal to a gate terminal, but to ensure the electric field is essentially uniform level between the gate and drain terminals.


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