The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2024
Filed:
Jul. 28, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Ching-Sheng Chu, Baoshan Township, TW;
Dun-Nian Yaung, Taipei, TW;
Yu-Cheng Tsai, Tainan, TW;
Meng-Hsien Lin, Tainan, TW;
Ching-Chung Su, Tainan, TW;
Jen-Cheng Liu, Hsin-Chu, TW;
Wen-De Wang, Minsyong Township, TW;
Guan-Hua Chen, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.