The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Jul. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hung-Jui Kuo, Hsinchu, TW;

Hui-Jung Tsai, Hsinchu, TW;

Chia-Wei Wang, Hsinchu, TW;

Yu-Tzu Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 24/82 (2013.01); H01L 21/4846 (2013.01); H01L 21/568 (2013.01); H01L 24/03 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 21/78 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/03914 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/24147 (2013.01); H01L 2224/24175 (2013.01); H01L 2224/25171 (2013.01); H01L 2224/2939 (2013.01); H01L 2224/73209 (2013.01); H01L 2224/82005 (2013.01); H01L 2224/82106 (2013.01);
Abstract

A method of forming a redistribution structure includes providing a dielectric layer. The dielectric layer is patterned to form a plurality of via openings. A seed layer is formed on the dielectric layer and filling in the plurality of via openings. A patterned conductive layer is formed a on the seed layer, wherein a portion of the seed layer is exposed by the patterned conductive layer. The portion of the seed layer is removed by using an etching solution, thereby forming a plurality of conductive lines and a plurality of vias. During the removing the portion of the seed layer, an etch rate of the patterned conductive layer is less than an etch rate of the seed layer.


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