The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

May. 16, 2022
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Zhuoqiang Jia, Mountain View, CA (US);

Leo Xing, Shanghai, CN;

Xian Liu, Sunnyvale, CA (US);

Serguei Jourba, Aix en Provence, FR;

Nhan Do, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/49 (2023.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H10B 41/49 (2023.02); H01L 29/40114 (2019.08); H01L 29/66825 (2013.01); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H01L 29/42328 (2013.01);
Abstract

A method of forming a device on a semiconductor substrate having first, second, third and dummy areas, includes recessing the substrate upper surface in the first, second and dummy areas, forming a first conductive layer over the substrate, removing the first conductive layer from the third area and a second portion of the dummy area, forming a first insulation layer over the substrate, forming first trenches through the first insulation layer and into the substrate in the third area and the second portion of the dummy area, forming second trenches through the first insulation layer, the first conductive layer and into the substrate in the first and second areas and a first portion of the dummy area, and filling the first and second trenches with insulation material. Then, memory cells are formed in the first area, HV devices in the second area and logic devices in the third area.


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