The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Sep. 22, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shan-Mei Liao, Hsinchu, TW;

Yung-Hsiang Chan, Hsinchu, TW;

Yao-Teng Chuang, Hsinchu, TW;

Jian-Hao Chen, Hsinchu, TW;

Kuo-Feng Yu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/15 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/152 (2013.01); H01L 21/823857 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/517 (2013.01); H01L 29/66742 (2013.01); H01L 29/7869 (2013.01);
Abstract

A method includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and merging between vertically adjacent portions of the first gate dielectric layer, and a second dipole layer surrounding the second gate dielectric layer and merging between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; after the removing of the first dipole layer, conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.


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