The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

May. 26, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Akihiro Horibe, Yokohama, JP;

Takahito Watanabe, Yokohama, JP;

Toyohiro Aoki, Yokohama, JP;

Takashi Hisada, Hachiouji, JP;

Hiroyuki Mori, Yasu, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 23/538 (2013.01); H01L 24/75 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 24/92 (2013.01); H01L 2224/75101 (2013.01); H01L 2224/75755 (2013.01); H01L 2224/75981 (2013.01); H01L 2224/81054 (2013.01); H01L 2224/81136 (2013.01); H01L 2224/83951 (2013.01); H01L 2224/92125 (2013.01);
Abstract

Interconnecting a first chip and a second chip includes mounting the first and second chips to a chip handler having an opening and at least one support surface. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The first surface of the first chip and the first surface of the second chip mounted to the chip handler are supported by the at least one support surface of the chip handler. The first and second chips are placed on a chip support member with the chip handler from the second surfaces. A bridge member is inserted by a bridge handler through the opening of the chip handler to place the bridge member onto the first sets of terminals of the first and second chips that are exposed from the opening.


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