The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Mar. 29, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hung-Hua Lin, Taipei, TW;

Chia-Ming Hung, Taipei, TW;

Xin-Hua Huang, Xihu Township, TW;

Yuan-Chih Hsieh, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81C 3/00 (2006.01); B81B 3/00 (2006.01); B81B 7/00 (2006.01); B81B 7/02 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B81C 3/001 (2013.01); B81B 7/0006 (2013.01); B81B 2203/0127 (2013.01); B81B 2207/07 (2013.01); B81C 2201/0176 (2013.01); B81C 2203/019 (2013.01); B81C 2203/037 (2013.01);
Abstract

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, where the method includes forming an interconnect structure over a first substrate. A dielectric structure is formed over the interconnect structure. The dielectric structure comprises opposing sidewalls defining an opening. A conductive bonding structure is formed on a second substrate. A bonding process is performed to bond the conductive bonding structure to the interconnect structure. The conductive bonding structure is disposed in the opening. The bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conducive bonding structure and the opposing sidewalls of the dielectric structure.


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