The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2024

Filed:

Sep. 27, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Andrew Gaul, Halfmoon, NY (US);

Julien Frougier, Albany, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Andrew M. Greene, Slingerlands, NY (US);

Christopher J. Waskiewicz, Rexford, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); H01L 29/0665 (2013.01); H01L 29/66477 (2013.01); H01L 29/78696 (2013.01);
Abstract

Semiconductor structures are disclosed which comprise semiconductor devices having thin multi-layer channel stacks. In one example, a semiconductor structure comprises a gate structure comprising a multi-layer channel stack. The multi-layer channel stack comprises a first dielectric layer, a second dielectric layer, and a channel layer disposed between the first and second dielectric layers. The semiconductor structure further comprises a first source/drain region disposed on a first side of the gate structure and in electrical contact with a first end portion of the multi-layer channel stack and a second source/drain region disposed on a second side of the gate structure and in electrical contact with a second end portion of the multi-layer channel stack.


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