The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2024

Filed:

Jul. 06, 2022
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Kun Zhang, Wuhan, CN;

Linchun Wu, Wuhan, CN;

Wenxi Zhou, Wuhan, CN;

Zhiliang Xia, Wuhan, CN;

Zongliang Huo, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack comprising interleaved conductive layers and dielectric layers, a plurality of semiconductor layers contacted with each other and located adjacent to the memory stack, a plurality of channel structures each extending vertically through the memory stack and at least one of the semiconductor layers, a source contact in contact with at least one of the semiconductor layers, and a contact pad located on one side of the semiconductor layers that are away from the memory stack.


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