The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Dec. 06, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Che Chi Shih, Taoyuan, TW;

Hsin Yang Hung, New Taipei, TW;

Ku-Feng Yang, Baoshan Township, TW;

Wei-Yen Woon, Taoyuan, TW;

Szuya Liao, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/456 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed. A contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.


Find Patent Forward Citations

Loading…