The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Jun. 08, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Sheng-Chan Li, Tainan, TW;

Cheng-Hsien Chou, Tainan, TW;

Sheng-Chau Chen, Tainan, TW;

Cheng-Yuan Tsai, Chu-Pei, TW;

Kuo-Ming Wu, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/3185 (2013.01); H01L 21/56 (2013.01); H01L 21/76829 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H01L 25/0657 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.


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