The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2024
Filed:
May. 15, 2023
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Chun-Chiang Chen, Hsinchu, TW;
Chun-Ting Wu, Kaohsiung, TW;
Ching-Hou Su, Hsinchu, TW;
Chih-Pin Wang, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76832 (2013.01); H01L 21/02274 (2013.01); H01L 21/76834 (2013.01); H01L 23/5226 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13024 (2013.01);
Abstract
An integrated circuit (IC) structure includes a substrate, an interconnect structure, metal lines, a liner, a protecting layer, and a nitride-free passivation layer. The interconnect structure is over the substrate. The metal lines are over the interconnect structure. The liner is conformally formed on the metal lines. The protecting layer is over the liner. The nitride-free passivation layer continuously extends from the liner to the protecting layer and forms an interface with the liner.