The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2024
Filed:
Apr. 28, 2023
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Yen-Chieh Huang, Hsinchu, TW;
Po-Ting Lin, Hsinchu, TW;
Hai-Ching Chen, Hsinchu, TW;
Sai-Hooi Yeong, Zhubei, TW;
Yu-Ming Lin, Hsinchu, TW;
Chung-Te Lin, Tainan, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 29/786 (2006.01); H10B 51/20 (2023.01);
U.S. Cl.
CPC ...
H01L 29/78391 (2014.09); H01L 29/4908 (2013.01); H01L 29/78642 (2013.01); H01L 29/78693 (2013.01); H10B 51/20 (2023.02);
Abstract
A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.