The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Apr. 04, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tzu-Yu Chen, Kaohsiung, TW;

Kuo-Chi Tu, Hsinchu, TW;

Fu-Chen Chang, New Taipei, TW;

Chih-Hsiang Chang, Taichung, TW;

Sheng-Hung Shih, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); G11C 11/22 (2006.01); H01L 49/02 (2006.01); H10B 53/10 (2023.01); H10B 53/30 (2023.01);
U.S. Cl.
CPC ...
H10B 53/30 (2023.02); G11C 11/221 (2013.01); H01L 28/56 (2013.01); H01L 28/75 (2013.01); H10B 53/10 (2023.02);
Abstract

In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.


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