The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2024
Filed:
Nov. 07, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Chih-Liang Chen, Hsinchu, TW;
Chih-Ming Lai, Hsinchu, TW;
Ching-Wei Tsai, Hsinchu, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
Jiann-Tyng Tzeng, Hsin Chu, TW;
Kuo-Cheng Chiang, Zhubei, TW;
Ru-Gun Liu, Zhubei, TW;
Wei-Hao Wu, Hsinchu, TW;
Yi-Hsiung Lin, Zhubei, TW;
Chia-Hao Chang, Hsinchu, TW;
Lei-Chun Chou, Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.