The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Mar. 06, 2019
Applicant:

Hitachi High-tech Corporation, Tokyo, JP;

Inventors:

Takashi Hiroi, Tokyo, JP;

Nobuaki Hirose, Tokyo, JP;

Takahiro Urano, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2022.01); G06T 7/00 (2017.01); G06T 7/73 (2017.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67288 (2013.01); G06T 7/001 (2013.01); G06T 7/74 (2017.01); G06T 2200/24 (2013.01); G06T 2207/30148 (2013.01);
Abstract

The objective of the present invention is provide a defect inspection apparatus that increases defect position precision and can easily align a coordinate origin offset between a reviewing apparatus and the defect inspection apparatus, even when design data cannot be obtained or it is difficult to sufficiently use the design data. The defect inspection apparatus according to the present invention acquires a wafer swath image necessary for inspection, and uses the swath image to detect defects and calculate a positional deviation amount. During the calculation of the positional deviation amount, a template pattern is acquired from one arbitrary swath image via an image processing unit, and the template pattern and a plurality of swath images of the entire wafer are compared, whereby the positional deviation amount for a position corresponding to the template pattern on the wafer is calculated. For positions at which the template pattern is not present, an interpolated positional deviation amount is calculated by executing an interpolation operation by using the calculated positional deviation amount. A defect position is corrected on the basis of the positional deviation amount and the interpolated positional deviation amount, or by using a positional deviation map in which these positional deviation amounts have been mapped on the entire wafer.


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