The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Sep. 08, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Julien Frougier, Albany, NY (US);

Karthik Yogendra, Albany, NY (US);

Dimitri Houssameddine, Sunnyvale, CA (US);

Kangguo Cheng, Schenectady, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01);
U.S. Cl.
CPC ...
G11C 11/161 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02);
Abstract

An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode can be made from a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.


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