The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2024
Filed:
Aug. 24, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Sumit Ashtekar, Portland, OR (US);
Rahul Ramaswamy, Portland, OR (US);
Walid Hafez, Portland, OR (US);
Hector M. Saavedra Garcia, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01H 85/02 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 20/20 (2023.01);
U.S. Cl.
CPC ...
H10B 20/20 (2023.02); H01H 85/0241 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01H 2085/0283 (2013.01);
Abstract
A device structure includes a first gate on a first fin, a second gate on a second fin, where the second gate is spaced apart from the first gate by a distance. A fuse spans the distance and is in contact with the first gate and the second gate. A first dielectric is between the first fin and the second fin, where the first dielectric is in contact with, and below, the fuse and a second dielectric is between the first gate and the second gate, where the second dielectric is on the fuse.