The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2024
Filed:
Mar. 12, 2021
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Chung-Huai Chang, Taichung, TW;
Chao-Hsun Wang, Taoyuan, TW;
Kuo-Yi Chao, Hsinchu, TW;
Mei-Yun Wang, Chupei, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/76838 (2013.01); H01L 21/76847 (2013.01); H01L 21/823828 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/665 (2013.01); H01L 29/7848 (2013.01);
Abstract
A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure, and a gate spacer layer formed on a sidewall of the gate structure. The FinFET device structure includes a gate contact structure formed over the gate structure, and a first isolation layer surrounding the gate contact structure. A bottom surface of the first isolation layer is lower than a top surface of the gate spacer layer.