The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2024

Filed:

Jun. 07, 2022
Applicant:

Flosfia Inc., Kyoto, JP;

Inventors:

Mitsuru Okigawa, Kyoto, JP;

Fujio Okui, Kyoto, JP;

Yasushi Higuchi, Kyoto, JP;

Koji Amazutsumi, Kyoto, JP;

Hidetaka Shibata, Kyoto, JP;

Yuji Kato, Kyoto, JP;

Atsushi Terai, Kyoto, JP;

Assignee:

FLOSFIA INC., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/47 (2006.01); H01L 29/872 (2006.01);
U.S. Cl.
CPC ...
H01L 29/475 (2013.01); H01L 29/0649 (2013.01); H01L 29/872 (2013.01);
Abstract

Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n−-type semiconductor layer that is placed on the n+-type semiconductor layer, the n−-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n−-type semiconductor layer, the high-resistance layer having a bottom surface located at a distance of less than 1.5 μm from an upper surface of the n+-type semiconductor layer; and a Schottky electrode that forms a Schottky junction with the n−-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.


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