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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12107012 B1

PDFFull Text
Date of Patent:
Oct. 01, 2024

Filed:

Jul. 24, 2023

Method for forming fin field effect transistor device structure

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shang-Wen Chang, Jhubei, TW;

Yi-Hsiung Lin, Zhubei, TW;

Yi-Hsun Chiu, Zhubei, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Mohammed R Alam

Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/76876 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

A method for forming a fin field effect transistor device structure is provided. The method includes forming a first spacer layer over a first fin structure and a second fin structure. The method also includes forming a power rail between the first fin structure and the second fin structure. The method further includes forming a second spacer layer over the first spacer layer and the power rail. In addition, the method includes forming a fin isolation structure over the power rail between the first fin structure and the second fin structure. The method also includes forming an epitaxial structure over the first fin structure and the second fin structure. The method further includes forming an inter-layer dielectric structure covering the epitaxial structure. In addition, the method includes forming an opening exposing the epitaxial structure, the power rail and the fin isolation structure. The method also includes filling the opening with a first contact structure.

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