The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2024
Filed:
Mar. 29, 2021
Applicant:
Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;
Inventors:
Chi-Fu Lin, Zhubei, TW;
Cheng-Hsin Chen, Toufen, TW;
Ming-I Hsu, Taoyuan, TW;
Kun-Ming Huang, Taipei, TW;
Chien-Li Kuo, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 21/225 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7394 (2013.01); H01L 21/225 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/66325 (2013.01);
Abstract
A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.