The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Apr. 13, 2023
Applicant:

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Janbo Zhang, Quanzhou, CN;

Chao-Wei Lin, Quanzhou, CN;

Chia-Yi Chu, Quanzhou, CN;

Yu-Cheng Tung, Quanzhou, CN;

Ken-Li Chen, Quanzhou, CN;

Tsung-Wen Chen, Quanzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/02 (2006.01); H01L 21/764 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/0217 (2013.01); H01L 21/764 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 23/5329 (2013.01); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02);
Abstract

A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.


Find Patent Forward Citations

Loading…