Memory device and multi-pass program operation thereof

Abstract

In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2levels, where N is an integer greater than 1. The level corresponds to one of 2pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a target memory cell of the memory cells into one of x intermediate levels based on all pages of N pages of the piece of N-bits data to be stored in the target memory cell, where x is an integer smaller than 2. The peripheral circuit is also configured to program, in a second pass after the first pass, the target memory cell into one of the 2levels based on all pages of the N pages of the piece of N-bits data to be stored in the target memory cell.