The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Jun. 29, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hung-Ling Shih, Tainan, TW;

Yong-Shiuan Tsair, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); G11C 29/14 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H10B 41/30 (2023.01); H10B 41/42 (2023.01);
U.S. Cl.
CPC ...
H10B 41/42 (2023.02); G11C 29/14 (2013.01); H01L 21/31116 (2013.01); H01L 21/32137 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 29/0847 (2013.01); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H10B 41/30 (2023.02); H01L 29/66545 (2013.01);
Abstract

Various embodiments of the present application are directed to a method for forming an integrated circuit (IC) comprising forming a multilayer film to form a plurality of memory cell structures disposed over a substrate and a plurality of memory test structures next to the memory cell structures. A memory test structure comprises a dummy control gate separated from the substrate by a dummy floating gate. The method further comprises forming a conductive floating gate test contact via along sidewalls of the dummy control gate and the dummy floating gate.


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