The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Xuan Huang, Hsinchu, TW;

Wang-Chun Huang, Hsinchu, TW;

Yi-Bo Liao, Hsinchu, TW;

Cheng-Ting Chung, Hsinchu, TW;

Hou-Yu Chen, Hsinchu County, TW;

Kuan-Lun Cheng, Hsin-Chu, TW;

Wei Ju Lee, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/41 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41733 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/66742 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/66545 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.


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