The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Aug. 28, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Sung-Hsin Yang, Hsinchu, TW;

Jung-Chi Jeng, Tainan, TW;

Ru-Shang Hsiao, Jhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/8238 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0688 (2013.01); H01L 21/82385 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/092 (2013.01); H01L 29/401 (2013.01); H01L 29/42356 (2013.01); H01L 29/42376 (2013.01); H01L 29/66545 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first three-dimensional semiconductor structure of a first conductivity type protruding from a surface of the semiconductor substrate. The semiconductor device includes a second three-dimensional semiconductor structure of a second conductivity type protruding from the surface of the semiconductor substrate. The semiconductor device includes a first transistor having a first source/drain structure formed in the first three-dimensional semiconductor structure, a second source/drain structure formed in the second three-dimensional semiconductor structure, a first gate structure straddling a first portion of the first three-dimensional semiconductor structure and a first portion of the second three-dimensional semiconductor structure, and a second gate structure straddling a second portion of the second three-dimensional semiconductor structure.


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